This application claims the benefit of Korean Patent Application No. 2004-51525, filed on Jul. 2, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a synchronous random access memory (SRAM) device employing a virtual rail scheme that is stable against various process-voltage-temperature (PVT) variations.
2. Description of the Related Art
FIG. 1 is a circuit diagram of an SRAM cell 101, which is generally used in an SRAM memory array and comprised of 6 transistors. The SRAM cell 101 is well known as a 6T SRAM cell. In the SRAM cell 101, NMOS transistors N1 and N2 are connected between a ground voltage VSS and a node A and between the ground voltage VSS and a node B, respectively, and the nodes A and B are connected to a power supply voltage VDD via PMOS transistors P1 and P2, respectively. The node A is connected to gates of the transistors P2 and N2, and the node B is connected to gates of the transistors P1 and N1.
The SRAM cell 101 stores data. More specifically, the SRAM cell 101 stores a voltage level in a flipflop that is formed of two cross connected inverters. One of the crossed inverters is comprised of transistors P1 and N1, and the other is comprised of transistors P2 and N2. For example, when the node A has a voltage level about the same as the ground voltage VSS, that is, is logic low, the transistor P2 is turned on, and the transistor N2 is turned off, so that the node B is pulled up to nearly the level of the power supply voltage VDD and enters into a logic high state. When the node B is logic high, the transistor P1 is turned off, and the transistor N1 is turned on, so that the node A is pulled down to the ground voltage VSS and enters into a logic low state. In this way, the SRAM cell 101 is continuously latched.
The nodes A and B are connected to a bitline BL and a complementary bitline /BL, respectively, via NMOS transistors N3 and N4, respectively. The NMOS transistors N3 and N4 are referred to as access transistors or pass transistors. Gates of the NMOS transistors N3 and N4 are connected to a wordline WL that enables reading and writing operations. If the node A is logic low and the wordline WL is enabled to a logic high level, a current path from the bitline BL to the ground voltage VSS via the pass transistor N3 and the transistor N1 is formed, and the logic low state of the node A is read out to the bitline BL.
If the node A is logic low and the wordline WL is logic low, a leakage current path 103 from the bitline BL to the ground voltage VSS via the pass transistor N3 and the transistor N1 is formed in the SRAM cell 101.
As the size of SRAM cells continues to decrease, the amount of read current provided by the SRAM cell decreases. In particular, the read current decreases with a decrease in power supply voltage VDD due to technical advancement. In contrast with the decrease of the read current, the magnitude of the leakage current increases. With increased leakage current, the reading of data from an SRAM cell becomes more difficult, and an approach for of reducing the leakage current from each SRAM cell is required.
Techniques for reducing the leakage current from an SRAM cell are disclosed in U.S. Pat. Nos. 6,560,139 and 6,549,453.
In an SRAM cell of U.S. Pat. No. 6,560,139 shown in FIG. 2, sources of pull-down transistors N1 and N2 are not directly connected to a ground voltage VSS but connected to the ground voltage VSS via a bias device 203. The bias device 203 is a transistor and operates to increase the voltages at the sources of the pull-down transistors N1 and N2 by a voltage drop across a channel of the bias transistor 203 that is gated to a power supply voltage VDD and turned on. When the voltages at the sources of the pull-down transistors N1 and N2 increase, a gate-source voltage of the transistors N1 and N2 is negative. Hence, reverse-biased source junctions deplete channels of the transistors N1 and N2, thereby increasing the threshold voltage Vt. Due to the increase of the threshold voltage Vt, read current is slightly reduced, but leakage current is reduced exponentially.
In SRAM cell array 200 of U.S. Pat. No. 6,549,453 shown in FIG. 3, a voltage of a VL node is increased from a ground voltage VSS by a threshold voltage Vt of an NMOS transistor using an NMOS transistor 208 diode-connected to a switching portion 206. Hence, as in the above U.S. Pat. No. '139, the leakage current is reduced, and the voltage swing width necessary for reversing a bit of a cell node from 0 to 1 or vice versa is also reduced. Also, the voltage of a VH node is decreased from the power supply voltage VDD by the threshold voltage Vt of a PMOS transistor using a PMOS transistor 214 diode-connected to a switching portion 210, and the voltage swing width necessary for reversing the bit of the cell node from 0 to 1 or vice versa is reduced.
In a virtual rail technique where a power supply voltage is lowered to a predetermined voltage and a ground voltage VSS is increased to a predetermined voltage to achieve a low leakage current mode of an SRAM, the lowered power supply voltage VH and the increased ground voltage VL are determined depending on the amount of current leaking from each SRAM cell and a weak turn-on current of the transistors 208 and 214, which have diode characteristics.
When a low leakage current SRAM is applied to a system-on-chip (SOC) circuit configuration, the ranges of virtual rails VH and VL of the power supply voltage VDD and the ground voltage VSS are changed due to the influence of various voltage and temperature characteristics on the operation of the SOC. Further, during the manufacture of an SOC semiconductor device, the ranges of virtual rails VH and VL of the power supply voltage VDD and the ground voltage VSS are changed due to an influence of process parameters. The results of a simulation of the resulting virtual rail voltages depending on process, voltage, and temperature, that is, PVT, conditions, is illustrated in FIG. 4.
FIG. 4 illustrates a virtual rail distribution versus PVT conditions in which a level of a power supply voltage VDD varies, for example 1.35V, 1.2V, 1.1V, 1.05V, etc., a temperature vary, for example, −55° C., 25° C., 125° C., etc., and operations of PMOS and NMOS transistors varies, for example, fast-fast (F-F), fast-slow (F-S), slow-fast (S-F), and slow-slow (S-S). Referring to FIG. 4, a virtual power supply voltage VH and a virtual ground voltage VL severely fluctuate according to the PVT conditions. In particular, the virtual power supply voltage VH and the virtual ground voltage VL have a maximum difference of ΔA and a minimum difference of ΔB. At portion ΔA, read current of an SRAM cell increases, so that the SRAM cell can operate stably but the leakage current increases. At portion ΔB, the leakage current is small but the read current of the SRAM cell decreases, so that the SRAM cell performs unstable reading operations.